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Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from semantic specifications and descriptions thereof |
Carlos Dangelo, Vijay Nagasamy, Sreeranga P. Rajan |
1999-03-09 |
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Method and apparatus for verifying asynchronous circuits using static timing analysis and dynamic functional simulation |
Pierrick Pedron, Franklin J. Malloy, Oz Levia |
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ECAD system for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic descriptions thereof |
Carlos Dangelo, Vijay Nagasamy, Sreeranga P. Rajan |
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| 5222030 |
Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof |
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1993-06-22 |
