Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12140628 | Integrating machine learning delay estimation in FPGA-based emulation systems | Yu YANG, Jiajun Fan, Vinod Kumar Nakkala, Vijay Sundaresan, Jianfeng Huang | 2024-11-12 |
| 11966677 | Emulation performance analysis using abstract timing graph representation | Melvyn Goveas, Ribhu Mittal, Wen-Chi Feng | 2024-04-23 |
| 11860227 | Machine learning delay estimation for emulation systems | Yu YANG, Jiajun Fan, Vinod Kumar Nakkala, Vijay Sundaresan, Jianfeng Huang | 2024-01-02 |
| 9672307 | Clock placement for programmable logic devices | Chih-Chung Chen | 2017-06-06 |
| 9390220 | Bus-based clock to out path optimization | Jun Zhao | 2016-07-12 |
| 9330217 | Holdtime correction using input/output block delay | Jun Zhao | 2016-05-03 |
| 8181139 | Multi-priority placement for configuring programmable logic devices | Xiaotao Chen, Eric Ting, Ruofan Xu, Jun Zhao | 2012-05-15 |
| 7757198 | Scan chain systems and methods for programmable logic devices | Jun Zhao, Eric Ting | 2010-07-13 |