Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6294925 | Programmable logic device | Albert Chan, Cyrus Y. Tsui, Rafael C. Camarota | 2001-09-25 |
| 6278311 | Method for minimizing instantaneous currents when driving bus signals | Albert Chan, Cyrus Y. Tsui, Rafael C. Camarota | 2001-08-21 |
| 6255847 | Programmable logic device | Albert Chan, Cyrus Y. Tsui, Rafael C. Camarota | 2001-07-03 |
| 6229336 | Programmable integrated circuit device with slew control and skew control | Bradley Felton, Albert Chan, Cyrus Y. Tsui, Rafael C. Camarota | 2001-05-08 |
| 6191609 | Combination of global clock and localized clocks | Albert Chan, Cyrus Y. Tsui, Allan T. Davidson | 2001-02-20 |
| 6133750 | Combination of global clock and localized clocks | Albert Chan, Cyrus Y. Tsui, Allan T. Davidson | 2000-10-17 |
| 6128770 | Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block) | Om P. Agrawal, Michael J. Wright | 2000-10-03 |
| 6104207 | Programmable logic device | Albert Chan, Cyrus Y. Tsui | 2000-08-15 |
| 6066977 | Programmable output voltage levels | Bradley Felton, Albert Chan, Cyrus Y. Tsui, Rafael C. Camarota | 2000-05-23 |
| 5740069 | Logic device (PLD) having direct connections between configurable logic blocks (CLBs) and configurable input/output blocks (IOBs) | Om P. Agrawal, Michael J. Wright | 1998-04-14 |
| 5598346 | Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks | Om P. Agrawal, Michael J. Wright | 1997-01-28 |
| 5587921 | Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer | Om P. Agrawal, Michael J. Wright | 1996-12-24 |
| 5586044 | Array of configurable logic blocks including cascadable lookup tables | Om P. Agrawal, Michael J. Wright | 1996-12-17 |
| 5490074 | Constant delay interconnect for coupling configurable logic blocks | Om P. Agrawal, Michael J. Wright | 1996-02-06 |
| 5469368 | Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output of second lookup with an alternate function output | Om P. Agrawal, Michael J. Wright | 1995-11-21 |
| 5422823 | Programmable gate array device having cascaded means for function definition | Om P. Agrawal, Michael J. Wright | 1995-06-06 |
| 5412260 | Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device | Cyrus Y. Tsui, Albert Chan, Kapil Shankar | 1995-05-02 |
| 5394033 | Structure and method for implementing hierarchical routing pools in a programmable logic circuit | Cyrus Y. Tsui, Chanchi J. Cheng, Ming-Chuan Hsu | 1995-02-28 |
| 5359536 | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block | Om P. Agrawal, Michael J. Wright | 1994-10-25 |
| 5336951 | Structure and method for multiplexing pins for in-system programming | Gregg R. Josephson, Roy D. Darling, Chan-Chi Jason Cheng | 1994-08-09 |
| 5329460 | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block | Om P. Agrawal, Michael J. Wright | 1994-07-12 |
| 5260881 | Programmable gate array with improved configurable logic block | Om P. Agrawal, Michael J. Wright | 1993-11-09 |
| 5237218 | Structure and method for multiplexing pins for in-system programming | Gregg R. Josephson, Roy D. Darling, Chan-Chi Jason Cheng | 1993-08-17 |
| 5233539 | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block | Om P. Agrawal, Michael J. Wright | 1993-08-03 |
| 5212652 | Programmable gate array with improved interconnect structure | Om P. Agrawal, Michael J. Wright | 1993-05-18 |