Issued Patents All Time
Showing 26–39 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6429687 | Semiconductor integrated circuit device | Fujio Ishihara, Yukihiro Fujimoto | 2002-08-06 |
| 6414525 | I/O interface circuit, semiconductor chip and semiconductor system | — | 2002-07-02 |
| 6324106 | Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device | — | 2001-11-27 |
| 6278300 | I/O interface circuit, semiconductor chip and semiconductor system | — | 2001-08-21 |
| 6246617 | Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device | — | 2001-06-12 |
| 5991230 | Synchronous random access memory | — | 1999-11-23 |
| 5517454 | Semiconductor memory device having refresh circuits | Katsuhiko Sato, Kiyofumi Ochii | 1996-05-14 |
| 5512772 | Semiconductor device having bipolar transistor and MOS transistor | Takeo Maeda, Hiroshi Momose, Masataka Matsui | 1996-04-30 |
| 5399894 | Semiconductor device having bipolar transistor and MOS transistor | Takeo Maeda, Hiroshi Momose, Masataka Matsui | 1995-03-21 |
| 5331225 | BiCMOS logic circuit with bipolar transistor and MOS transistor formed on the same semiconductor substrate | Masataka Matsui | 1994-07-19 |
| 5331233 | Sense amplifier circuit for reducing transmission delay in data line | — | 1994-07-19 |
| 5049806 | Band-gap type voltage generating circuit for an ECL circuit | Masataka Matsui | 1991-09-17 |
| 5027009 | Semiconductor logic circuit with a bipolar current mirror arrangement | Masataka Matsui | 1991-06-25 |
| 4992681 | Logic level converting circuit | Masataka Matsui | 1991-02-12 |