Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5153699 | Semiconductor device | Tsukasa Shirotori, Kazuhiro Sawada | 1992-10-06 |
| 4984208 | Dynamic read/write memory with improved refreshing operation | Kazuhiro Sawada, Kazutaka Nogami | 1991-01-08 |
| 4974203 | Arrangement and construction of an output control circuit in a semiconductor memory device | — | 1990-11-27 |
| 4958326 | Semiconductor memory device having a function of simultaneously clearing part of memory data | — | 1990-09-18 |
| 4939695 | Virtual type static semiconductor memory device including refresh detector circuitry | Mitsuo Isobe, Kazuhiro Sawada, Kazutaka Nogami, Hisashi Ueno | 1990-07-03 |
| 4905192 | Semiconductor memory cell | Kazutaka Nogami | 1990-02-27 |
| 4866677 | Semiconductor memory device with multiple alternating decoders coupled to each word line | — | 1989-09-12 |
| 4857763 | MOS semiconductor integrated circuit in which the production of hot carriers near the drain of a short n channel conductivity type MOS transistor is decreased | Tetsuya Iizuka | 1989-08-15 |
| 4853654 | MOS semiconductor circuit | — | 1989-08-01 |
| 4853897 | Complementary semiconductor memory device | Kazutaka Nogami | 1989-08-01 |
| 4827453 | Semiconductor memory control circuit | Kazuhiro Sawada | 1989-05-02 |
| 4812735 | Intermediate potential generating circuit | Kazuhiro Sawada | 1989-03-14 |
| 4769792 | Semiconductor memory device with voltage bootstrap | Kazutaka Nogami, Syuso Fujii | 1988-09-06 |
| 4764901 | Semiconductor memory device capable of being accessed before completion of data output | — | 1988-08-16 |
| 4757217 | Refresh operation control circuit for semiconductor device | Kazuhiro Sawada, Kazutaka Nogami | 1988-07-12 |
| 4744063 | Static memory utilizing transition detectors to reduce power consumption | Takayuki Ohtani, Mitsuo Isobe, Tetsuya Iizuka | 1988-05-10 |
| 4740713 | MOS semiconductor integrated circuit in which the production of hot carriers near the drain of a short n channel conductivity type MOS transistor is decreased | Tetsuya Iizuka | 1988-04-26 |
| 4683382 | Power-saving voltage supply | Tetsuya Iizuka | 1987-07-28 |
| 4682306 | Self-refresh control circuit for dynamic semiconductor memory device | Tetsuya Iizuka | 1987-07-21 |
| 4677592 | Dynamic RAM | Tetsuya Iizuka | 1987-06-30 |
| 4618945 | Semiconductor memory device | Tetsuya Iizuka | 1986-10-21 |
| 4592026 | Memory device resistant to soft errors | Naohiro Matsukawa, Mitsuo Isobe | 1986-05-27 |
| 4587638 | Semiconductor memory device | Mitsuo Isobe, Kazuhiro Sawada, Tetsuya Iizuka, Takayuki Ohtani, Akira Aono | 1986-05-06 |
| 4555778 | Semiconductor memory device | — | 1985-11-26 |