Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12237014 | Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate | Toshiki Hisada, Dai Nakamura | 2025-02-25 |
| 12193225 | Semiconductor device | Sho Tokairin, Yoshinao Suzuki | 2025-01-07 |
| 11610630 | Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate | Toshiki Hisada, Dai Nakamura | 2023-03-21 |
| 10978151 | Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate | Toshiki Hisada, Dai Nakamura | 2021-04-13 |
| 10431309 | Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate | Toshiki Hisada, Dai Nakamura | 2019-10-01 |
| 10304538 | Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate | Toshiki Hisada, Dai Nakamura | 2019-05-28 |
| 10049745 | Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate | Toshiki Hisada, Dai Nakamura | 2018-08-14 |
| 9691484 | Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate | Toshiki Hisada, Dai Nakamura | 2017-06-27 |
| 9324432 | Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate | Toshiki Hisada, Dai Nakamura | 2016-04-26 |
| 8779844 | Semiconductor integrated circuit | Mai Muramoto | 2014-07-15 |
| 8659968 | Power supply circuit and semiconductor memory device including the power supply circuit | — | 2014-02-25 |
| 8630106 | Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate | Toshiki Hisada, Dai Nakamura | 2014-01-14 |