Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6118697 | Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing | Tooru Tanzawa, Nobuaki Otsuka, Shigeru Atsumi, Masao Kuriyama, Seiichi Mori +1 more | 2000-09-12 |
| 6108246 | Semiconductor memory device | Akira Umezawa, Hitoshi Shiga, Shigeru Atsumi | 2000-08-22 |
| 6052313 | Semiconductor integrated circuit device | Shigeru Atsumi, Masao Kuriyama, Akira Umezawa, Tadayuki Taura, Hidetoshi Saito | 2000-04-18 |
| 6041012 | Semiconductor integrated circuit device having a booster circuit and a storage device | Hitoshi Shiga, Shigeru Atsumi, Akira Umezawa | 2000-03-21 |
| 6041011 | Booster circuit and semiconductor memory device having the same | Akira Umezawa, Shigeru Atsumi | 2000-03-21 |
| 6034567 | Semiconductor integrated circuit device provided with a differential amplifier | Akira Umezawa, Shigeru Atsumi, Norihisa Arai, Ryo Sudo | 2000-03-07 |
| 6031397 | Negative voltage detection circuit offsetting fluctuation of detection level | — | 2000-02-29 |
| 5986935 | Semiconductor memory device with high voltage generation circuit | Yumiko Iyama, Shigeru Atsumi | 1999-11-16 |
| 5963500 | Semiconductor memory device | Tadayuki Taura, Shigeru Atsumi | 1999-10-05 |
| 5901083 | Nonvolatile semiconductor memory device | Shigeru Atsumi | 1999-05-04 |
| 5877985 | Intermediate voltage generating circuit and nonvolatile semiconductor memory having the same | Takeshi Miyaba | 1999-03-02 |
| 5734286 | Driving device of charge pump circuit and driving pulse generation method thereof | Yasuhisa Takeyama, Junichi Miyamoto, Yoshihisa Iwata, Hideko Oodaira | 1998-03-31 |
| 5568419 | Non-volatile semiconductor memory device and data erasing method therefor | Shigeru Atsumi, Masao Kuriyama, Akira Umezawa, Nobuaki Otsuka | 1996-10-22 |
| 5559744 | Semiconductor integrated circuit device having a test mode setting circuit | Masao Kuriyama | 1996-09-24 |
| 5428571 | Data latch circuit having non-volatile memory cell equipped with common floating gate and stress relaxing transistor | Shigeru Atsumi | 1995-06-27 |
| 5311470 | Data latch circuit having non-volatile memory cell | Shigeru Atsumi | 1994-05-10 |
| 5253201 | Writing control circuit employed in non-volatile semiconductor memory device | Shigeru Atsumi | 1993-10-12 |