TM

Thomas C. McDonald

IP Ip-First: 21 patents #4 of 27Top 15%
CT Centaur Technology: 10 patents #1 of 16Top 7%
VT Via Technologies: 9 patents #62 of 1,108Top 6%
GR Grindmaster: 1 patents #18 of 54Top 35%
IBM: 1 patents #44,794 of 70,183Top 65%
📍 Lodi, CA: #3 of 174 inventorsTop 2%
🗺 California: #10,163 of 386,348 inventorsTop 3%
Overall (All Time): #70,046 of 4,157,543Top 2%
43
Patents All Time

Issued Patents All Time

Showing 26–43 of 43 patents

Patent #TitleCo-InventorsDate
7185186 Apparatus and method for resolving deadlock fetch conditions involving branch target address cache 2007-02-27
7178010 Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack 2007-02-13
7165169 Speculative branch target address cache with selective override by secondary predictor based on branch instruction type G. Glenn Henry 2007-01-16
7165168 Microprocessor with branch target address cache update queue 2007-01-16
7162619 Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer G. Glenn Henry 2007-01-09
7159098 Selecting next instruction line buffer stage based on current instruction line boundary wraparound and branch target in buffer indicator G. Glenn Henry 2007-01-02
7159097 Apparatus and method for buffering instructions and late-generated related information using history of previous load/shifts 2007-01-02
7152154 Apparatus and method for invalidation of redundant branch target address cache entries 2006-12-19
7143269 Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessor 2006-11-28
7140196 Chilled beverage dispenser with cradle evaporator Thomas Joseph Pfeifer 2006-11-28
7134005 Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte G. Glenn Henry, Terry Parks 2006-11-07
7117347 Processor including fallback branch prediction mechanism for far jump and far call instructions Gerard M. Col 2006-10-03
6895498 Apparatus and method for target address replacement in speculative branch target address cache Terry Parks 2005-05-17
6886093 Speculative hybrid branch direction predictor G. Glenn Henry 2005-04-26
6823444 Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrap G. Glenn Henry 2004-11-23
6314514 Method and apparatus for correcting an internal call/return stack in a microprocessor that speculatively executes call and return instructions 2001-11-06
5831459 Method and system for adjusting a clock signal within electronic circuitry 1998-11-03
D283204 Garden hose water meter 1986-04-01