Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
PK

Peter Korger — 16 Patents

LSLsi: 12 patents #279 of 3,238Top 9%
NANapatech A/S: 3 patents #1 of 24Top 5%
Disney: 1 patents #4,015 of 6,686Top 65%
Overall (All Time): #284,196 of 4,157,543Top 7%
16 Patents All Time
Peter Korger has been granted 16 US patents. The first was granted in 2000 and the most recent in August 2016. Peter Korger ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Peter Korger in Aarhus, CO, DK.

Patents per Year

Patents granted per year, 2000 to 2016Bar chart with a peak of 4 patents in 2006.peak 42000: 1 patents20002002: 1 patents20022003: 3 patents20032004: 1 patents20042005: 2 patents20052006: 4 patents20062014: 1 patents20142015: 1 patents20152016: 2 patents2016

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9407581 Distributed processing of data frames by multiple adapters using time stamping and a central controller Peter Ekner 2016-08-02
9304961 Method and apparatus for transferring packets between interface control modules of line cards Jacob Jul Schroder, Claus F. Hoyer, Lars Froslev-Nielsen 2016-04-05 $3,397,000
8934341 Apparatus and a method of receiving and storing data packets controlled by a central controller 2015-01-13
8874809 Assembly and a method of receiving and storing data while saving bandwidth by controlling updating of fill levels of queues 2014-10-28
7065683 Long path at-speed testing David Sluiter, Robert W. Moss, Mark Jon Kwong, Christopher M. Giles 2006-06-20 $5,526,000
7032104 Configurable hardware register stack for CPU architectures 2006-04-18 $8,132,000
7028238 Input/output characterization chain for an integrated circuit Brian Schoner 2006-04-11 $3,438,000
6999542 Data ready indicator between different clock domains Robert W. Moss 2006-02-14 $2,607,000
6917561 Memory controller and method of aligning write data to a memory device Robert W. Moss 2005-07-12 $8,428,000
6880050 Storage device, system and method which can use tag bits to synchronize queuing between two clock domains, and detect valid entries within the storage device 2005-04-12 $3,219,000
6798186 Physical linearity test for integrated circuit delay lines Robert W. Moss 2004-09-28 $2,080,000
6646929 Methods and structure for read data synchronization with minimal latency Robert W. Moss 2003-11-11 $7,952,000
6600681 Method and apparatus for calibrating DQS qualification in a memory controller Robert W. Moss 2003-07-29 $19,188,000
6509762 Method and apparatus for measuring the phase of captured read data Robert W. Moss 2003-01-21 $15,965,000
6496043 Method and apparatus for measuring the phase of captured read data Robert W. Moss 2002-12-17 $2,785,000
6092159 Implementation of configurable on-chip fast memory using the data cache RAM Hartvig Ekner 2000-07-18 $20,251,000