KC

Kit M. Cham

HP HP: 5 patents #933 of 7,018Top 15%
AT Agilent Technologies: 3 patents #759 of 3,411Top 25%
AP Avago Technologies Fiber Ip (Singapore) Pte.: 2 patents #77 of 263Top 30%
AL Avago Technologies Limited: 1 patents #1 of 22Top 5%
AP Avego Technologies General Ip (Singapore) Pte.: 1 patents #1 of 21Top 5%
Overall (All Time): #420,744 of 4,157,543Top 15%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9106338 Dual-wavelength bidirectional optical communication system and method for communicating optical signals David Chak Wang Hui, Xiaozhong Wang, Bing Shao, Seng-Kum Chan, Ye Chen 2015-08-11
8195017 Consumer input/output (CIO) optical transceiver module for use in an active optical cable, an active optical cable that incorporates the CIO optical transceiver module, and a method Ronald Kaneshiro, Xiaozhong Wang, Paul Yu, Chung-Yi Su 2012-06-05
7653272 Highly parallel optical communication system with intracard and intercard communications Lisa Buckman 2010-01-26
7049570 Optical chip coupling system utilizing micromachine adjustable optical elements and a feedback circuit providing the micromachine with a feedback signal correlated to an optical signal parameter Frank Peters 2006-05-23
6526076 Integrated parallel channel optical monitoring for parallel optics transmitter Myunghee Lee, James J. Dudley, Stefano Therisod, Craig T. Cummings, Yu-Chun Chang +3 more 2003-02-25
6246436 Adjustable gain active pixel sensor Jane M. Lin, Eric Y. Chou 2001-06-12
6114739 Elevated pin diode active pixel sensor which includes a patterned doped semiconductor electrode Jeremy Alfred Theil, Min Cao, Dietrich W. Vook, Frederick Perner, Xin Sun +4 more 2000-09-05
5952686 Salient integration mode active pixel sensor Eric Y. Chou, Jane M. Lin 1999-09-14
5189310 BICMOS logic gate circuit and structures Robert E. Gleason 1993-02-23
4999523 BICMOS logic gate with higher pull-up voltage Robert E. Gleason 1991-03-12
4894694 MOSFET structure and method for making same Paul Vande Voorde 1990-01-16
4746624 Method for making an LDD MOSFET with a shifted buried layer and a blocking region Paul Vande Voorde 1988-05-24