Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12229064 | Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver | Ching-Hsiang Chang | 2025-02-18 |
| 11609872 | Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver | Ching-Hsiang Chang | 2023-03-21 |
| 11055241 | Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver | Ching-Hsiang Chang | 2021-07-06 |
| 11012087 | Encoding and decoding architecture for high speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof | Ching-Hsiang Chang | 2021-05-18 |
| 10574431 | Physical layer circuitry for multi-wire interface | Ching-Hsiang Chang, Yuan-Hsun Chang, Huai-Te Wang | 2020-02-25 |
| 10387360 | Integrated circuits adaptable to interchange between clock and data lanes for use in clock forward interface receiver | Pin-Hao Feng, Ching-Hsiang Chang | 2019-08-20 |
| 10263762 | Physical layer circuitry for multi-wire interface | Ching-Hsiang Chang, Yuan-Hsun Chang, Huai-Te Wang | 2019-04-16 |