YP

Yogesh Pandey

SY Synopsys: 3 patents #460 of 2,302Top 20%
Overall (All Time): #1,459,519 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10846455 Automatic definition and extraction of functional coverage metric for emulation-based verification Saptarshi Ghosh, Sivaprasad Acharya, Eduard Cerny 2020-11-24
9626468 Assertion extraction from design and its signal traces Eduard Cerny, Diganchal Chakraborty, Saptarshi Ghosh 2017-04-18
7925940 Enhancing speed of simulation of an IC design while testing scan circuitry Vijay Sankar, Manish Jain 2011-04-12