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Integrated circuit with scan-based debugging and debugging method thereof |
I-Chieh Han |
2009-05-12 |
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Apparatus and method for low power clock distribution |
Yung-Chieh Yu |
2007-02-20 |
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Method for performing multi-clock static timing analysis |
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2006-05-16 |
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Design flow method for integrated circuits |
Chun-Chih Yang |
2006-02-28 |
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Implementing method for buffering devices |
Yung-Chung Chang |
2005-11-22 |
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Circuitry cross-talk analysis with consideration of signal transitions |
Wen-Hao Hsueh |
2005-09-27 |
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Control chip with multiple-layer defer queue |
Sheng-Chung Wu |
2005-05-24 |
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Implementing for buffering devices in circuit layout to ensure same arriving time for clock signal from source root to output bonding pads |
Yung-Chung Chang |
2004-11-30 |
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Method for scheduling execution sequence of read and write operations |
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2004-03-23 |
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Phase lock loop (PLL) clock generator with programmable skew and frequency |
Jiin Lai, Jyhfong Lin, Hsin-Chieh Lin, Wei Wang |
2004-02-03 |
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Chipset with clock signal converting |
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2003-08-05 |
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Static timing analysis method for a circuit using generated clock |
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2003-05-13 |
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Chip testing system |
Chung-Pang Yu, Kuo-Ping Liu |
2002-01-01 |
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Method for controlling a process of writing data sent by a central processing unit to a memory by using a central processing unit interface |
Chia-Hsin Chen, Jiin Lai |
2001-07-31 |
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Gated clock tree synthesis method for the logic design |
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2000-02-01 |