WC

William D. Cox

VI Viasic: 14 patents #1 of 4Top 25%
QU Quicklogic: 10 patents #9 of 70Top 15%
TS Triad Semiconductor: 5 patents #1 of 5Top 20%
Google: 3 patents #8,000 of 22,993Top 35%
Overall (All Time): #144,251 of 4,157,543Top 4%
27
Patents All Time

Issued Patents All Time

Showing 25 most recent of 27 patents

Patent #TitleCo-InventorsDate
12120223 Scalable security for cryptographic ledgers via dynamic and unpredictable changes to quorum memberships Bo Zhu, Orest Bolohan, Sheldon I. Walfish 2024-10-15
11736278 Scalable security for cryptographic ledgers via dynamic and unpredictable changes to quorum memberships Bo Zhu, Orest Bolohan, Shabsi Walfish 2023-08-22
11258593 Scalable security for cryptographic ledgers via dynamic and unpredictable changes to quorum memberships Bo Zhu, Orest Bolohan, Sheldon I. Walfish 2022-02-22
7972907 Via configurable architecture for customization of analog circuitry in a semiconductor device James C. Kemerling, David Ihme 2011-07-05
7930670 Using selectable in-line inverters to reduce the number of inverters in a semiconductor design 2011-04-19
7692309 Configuring structured ASIC fabric using two non-adjacent via layers 2010-04-06
7626272 Via configurable architecture for customization of analog circuitry in a semiconductor device James C. Kemerling, David Ihme 2009-12-01
7595229 Configurable integrated circuit capacitor array using via mask layers David Ihme, James C. Kemerling 2009-09-29
7538580 Logic array devices having complex macro-cell architecture and methods facilitating use of same 2009-05-26
7449371 VIA configurable architecture for customization of analog circuitry in a semiconductor device James C. Kemerling, David Ihme 2008-11-11
7378874 Creating high-drive logic devices from standard gates with minimal use of custom masks Bhaskar Bharath 2008-05-27
7335966 Configurable integrated circuit capacitor array using via mask layers David Ihme, James C. Kemerling 2008-02-26
7334208 Customization of structured ASIC devices using pre-process extraction of routing information 2008-02-19
7248071 Logic array devices having complex macro-cell architecture and methods facilitating use of same 2007-07-24
6873185 Logic array devices having complex macro-cell architecture and methods facilitating use of same 2005-03-29
6693454 Distributed RAM in a logic array 2004-02-17
6580289 Cell architecture to reduce customization in a semiconductor device 2003-06-17
5900742 Interface cell for a programmable integrated circuit employing antifuses Paige A. Kolze, Kevin K. Yee 1999-05-04
5729468 Reducing propagation delays in a programmable device 1998-03-17
5682106 Logic module for field programmable gate array Benjamin W. Blair, Paige A. Kolze, Hua-Thye Chua 1997-10-28
5675502 Estimating propagation delays in a programmable device 1997-10-07
5552720 Method for simultaneous programming of multiple antifuses Mukesh T. Lulla 1996-09-03
5544070 Programmed programmable device and method for programming antifuses of a programmable device Andrew K. Chan, Richard J. Wong, James M. Apland, Kathryn E. Gordon 1996-08-06
5526276 Select set-based technology mapping method and apparatus Eric LEHMANN, Mukesh T. Lulla, Venkatesh Nathamuni 1996-06-11
5469077 Field programmable antifuse device and programming method therefor 1995-11-21