Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10529771 | Array of optoelectronic structures and fabrication thereof | Mattias B. Borg, Lukas Czornomaz, Veeresh V. Deshpande, Heike E. Riel, Heinz Schmid | 2020-01-07 |
| 10410926 | Fabricating contacts of a CMOS structure | Lukas Czornomaz, Veeresh V. Deshpande, Pouya Hashemi | 2019-09-10 |
| 10304934 | Fabricating raised source drain contacts of a CMOS structure | Lukas Czornomaz, Veeresh V. Deshpande | 2019-05-28 |
| 10256092 | Fabrication of semiconductor structures | Daniele Caimi, Lukas Czornomaz, Veeresh V. Deshpande, Jean Fompeyrine | 2019-04-09 |
| 10103234 | Fabricating raised source drain contacts of a CMOS structure | Lukas Czornomaz, Veeresh V. Deshpande | 2018-10-16 |
| 9997409 | Fabricating contacts of a CMOS structure | Lukas Czornomaz, Veeresh V. Deshpande, Pouya Hashemi | 2018-06-12 |
| 9984929 | Fabricating contacts of a CMOS structure | Lukas Czornomaz, Veeresh V. Deshpande, Pouya Hashemi | 2018-05-29 |
| 9953125 | Design/technology co-optimization platform for high-mobility channels CMOS technology | Daniele Caimi, Lukas Czornomaz, Veeresh V. Deshpande, Jean Fompeyrine | 2018-04-24 |
| 9923022 | Array of optoelectronic structures and fabrication thereof | Mattias B. Borg, Lukas Czornomaz, Veeresh V. Deshpande, Heike E. Riel, Heinz Schmid | 2018-03-20 |
| 9917164 | Fabricating raised source drain contacts of a CMOS structure | Lukas Czornomaz, Veeresh V. Deshpande | 2018-03-13 |
| 9881921 | Fabricating a dual gate stack of a CMOS structure | Lukas Czornomaz, Veeresh V. Deshpande, Jean Fompeyrine | 2018-01-30 |
| 9786664 | Fabricating a dual gate stack of a CMOS structure | Lukas Czornomaz, Veeresh V. Deshpande, Jean Fompeyrine | 2017-10-10 |
| 9704757 | Fabrication of semiconductor structures | Daniele Caimi, Lukas Czornomaz, Veeresh V. Deshpande, Jean Fompeyrine | 2017-07-11 |
| 9673104 | Fabrication of a CMOS structure | Lukas Czornomaz, Veeresh V. Deshpande, Jean Fompeyrine | 2017-06-06 |
| 9564452 | Fabrication of hybrid semiconductor circuits | Daniele Caimi, Lukas Czornomaz, Veeresh V. Deshpande, Jean Fompeyrine | 2017-02-07 |