Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6288453 | Alignment of openings in semiconductor fabrication | — | 2001-09-11 |
| 6239609 | Reduced voltage quiescent current test methodology for integrated circuits | Emery Sugasawara, Ronnie Vasishta | 2001-05-29 |
| 5998226 | Method and system for alignment of openings in semiconductor fabrication | — | 1999-12-07 |
| 5978197 | Testing ESD protection schemes in semiconductor integrated circuits | — | 1999-11-02 |