Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7372072 | Semiconductor wafer with test structure | Ramona Winter, Susanne Lachenmann, Sibina Sukman-Praehofer | 2008-05-13 |
| 7205567 | Semiconductor product having a semiconductor substrate and a test structure and method | Andreas Felber, Susanne Lachenmann, Sibina Sukman-Praehofer | 2007-04-17 |
| 6930325 | Test structure for improved vertical memory arrays | Bernhard Kowalski, Andreas Felber, Juergen Lindolf, Till Schloesser, Bernd Goebel | 2005-08-16 |
| 6930324 | Device architecture and process for improved vertical memory arrays | Bernhard Kowalski, Andreas Felber, Till Schloesser, Juergen Lindolf | 2005-08-16 |
| 6897077 | Test structure for determining a short circuit between trench capacitors in a memory cell array | Andreas Felber | 2005-05-24 |
| 6878965 | Test structure for determining a region of a deep trench outdiffusion in a memory cell array | Andreas Felber | 2005-04-12 |
| 6856562 | Test structure for measuring a junction resistance in a DRAM memory cell array | Susanne Lachenmann, Andreas Felber, Sibina Sukman | 2005-02-15 |
| 6853000 | Test structure for determining a doping region of an electrode connection between a trench capacitor and a selection transistor in a memory cell array | Andreas Felber | 2005-02-08 |
| 6838724 | Transistor array and semiconductor memory configuration fabricated with the transistor array | Bernhard Kowalski, Andreas Felber, Till Schlosser, Jürgen Lindolf | 2005-01-04 |
| 6656647 | Method for examining structures on a wafer | Guenther Gerstmeier, Frank Richter | 2003-12-02 |
| 6529031 | Integrated circuit configuration for testing transistors, and a semiconductor wafer having such a circuit configuration | Günter Gerstmeier | 2003-03-04 |
| 6484307 | Method for fabricating and checking structures of electronic circuits in a semiconductor substrate | Jürgen Karl, Martin Zibert | 2002-11-19 |