Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7322000 | Methods and apparatus for extending semiconductor chip testing with boundary scan registers | Loren J. Benecke, Joseph S. Vaccaro | 2008-01-22 |
| 7272767 | Methods and apparatus for incorporating IDDQ testing into logic BIST | Loren J. Benecke, Sribhaskar Mahadevan, Joseph S. Vaccaro | 2007-09-18 |
| 5199035 | Logic circuit for reliability and yield enhancement | David Lopez | 1993-03-30 |
| 4949341 | Built-in self test method for application specific integrated circuit libraries | David Lopez | 1990-08-14 |