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Multiple mode device implementation for programmable logic devices |
Brad Sharpe-Geisler, Senani Gunaratna |
2020-04-21 |
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Flexible ripple mode device implementation for programmable logic devices |
Brad Sharpe-Geisler, Senani Gunaratna |
2019-08-13 |
| 10141917 |
Multiple mode device implementation for programmable logic devices |
Brad Sharpe-Geisler, Senani Gunaratna |
2018-11-27 |
| 10079054 |
Selective power gating of routing resource configuration memory bits for programmable logic devices |
Senani Gunaratna, Brad Sharpe-Geisler, Ronald L. Cline |
2018-09-18 |
| 9735761 |
Flexible ripple mode device implementation for programmable logic devices |
Brad Sharpe-Geisler, Senani Gunaratna |
2017-08-15 |
| 9716491 |
Multiple mode device implementation for programmable logic devices |
Brad Sharpe-Geisler, Senani Gunaratna |
2017-07-25 |
| 9543950 |
High speed complementary NMOS LUT logic |
Brad Sharpe-Geisler, Senani Gunaratna |
2017-01-10 |
| 9252755 |
Shared logic for multiple registers with asynchronous initialization |
Brad Sharpe-Geisler, Senani Gunaratna |
2016-02-02 |
| 8370691 |
Testing of soft error detection logic for programmable logic devices |
Chan-Chi Jason Cheng, Qin Wei |
2013-02-05 |
| 8065574 |
Soft error detection logic testing systems and methods |
Chan-Chi Jason Cheng, Qin Wei |
2011-11-22 |
| 7576563 |
High fan-out signal routing systems and methods |
Qin Wei, Chan-Chi Jason Cheng, Brad Sharpe-Geisler |
2009-08-18 |
| 7401280 |
Self-verification of configuration memory in programmable logic devices |
Satwant Singh, Chi M. Nguyen, Ann Wu |
2008-07-15 |
| 7257750 |
Self-verification of configuration memory in programmable logic devices |
Satwant Singh, Chi M. Nguyen, Ann Wu |
2007-08-14 |