Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11879942 | Core and interface scan testing architecture and methodology | Banadappa Shivaray, Mahesh Rawal, Aviral Agarwal | 2024-01-23 |
| 9570195 | On chip characterization of timing parameters for memory ports | Abhijith Ramesh Kashyap | 2017-02-14 |
| 7448009 | Method of leakage optimization in integrated circuit design | — | 2008-11-04 |