RH

Richard T. Housley

Micron: 15 patents #1,089 of 6,345Top 20%
NT Nanya Technology: 4 patents #182 of 775Top 25%
📍 Boise, ID: #492 of 3,546 inventorsTop 15%
🗺 Idaho: #700 of 8,810 inventorsTop 8%
Overall (All Time): #213,821 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Showing 1–20 of 20 patents

Patent #TitleCo-InventorsDate
12230546 Wafer registration and overlay measurement systems and related methods Nikolay A. Mirin, Robert Dembi, Xiaosong Zhang, Jonathan D. Harms, Stephen J. Kramer 2025-02-18
11784077 Wafer overlay marks, overlay measurement systems, and related methods Denzil S. Frost, David S. Pratt, Trupti D. Gawai 2023-10-10
11520240 Wafer alignment markers, systems, and related methods Nikolay A. Mirin, Robert Dembi, Xiaosong Zhang, Jonathan D. Harms, Stephen J. Kramer 2022-12-06
11251096 Wafer registration and overlay measurement systems and related methods Nikolay A. Mirin, Robert Dembi, Xiaosong Zhang, Jonathan D. Harms, Stephen J. Kramer 2022-02-15
11075169 Integrated-circuitry overlay alignment mark, a substrate comprising an overlay alignment mark, a method of forming an overlay alignment mark in the fabrication of integrated circuitry, and a method of determining overlay alignment in the fabrication of integrated circuitry Denzil S. Frost, Jianming Zhou 2021-07-27
11009798 Wafer alignment markers, systems, and related methods Nikolay A. Mirin, Robert Dembi, Xiaosong Zhang, Jonathan D. Harms, Stephen J. Kramer 2021-05-18
10756022 Methods of alignment marking semiconductor wafers, and semiconductor packages having portions of alignment markings Jianming Zhou 2020-08-25
10461038 Methods of alignment marking semiconductor wafers, and semiconductor packages having portions of alignment markings Jianming Zhou 2019-10-29
9343114 Memory arrays and methods of forming electrical contacts 2016-05-17
9324721 Pitch-halving integrated circuit process David S. Pratt 2016-04-26
9245844 Pitch-halving integrated circuit process and integrated circuit structure made thereby David S. Pratt 2016-01-26
8796086 Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate Neal L. Davis, Ranjan Khurana 2014-08-05
8796786 Memory arrays and methods of forming electrical contacts 2014-08-05
8779918 Convulsive seizure detection and notification system 2014-07-15
8674522 Castle-like chop mask for forming staggered datalines for improved contact isolation and pattern thereof David S. Pratt 2014-03-18
8664077 Method for forming self-aligned overlay mark Vinay Nair, David S. Pratt, Christopher Hawk 2014-03-04
8586429 Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate Neal L. Davis, Ranjan Khurana 2013-11-19
8435859 Methods of forming electrical contacts 2013-05-07
8389353 Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate Neal L. Davis, Ranjan Khurana 2013-03-05
8039340 Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate Neal L. Davis, Ranjan Khurana 2011-10-18