Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8810280 | Low leakage spare gates for integrated circuits | Yongjun Zhang, Yongning SHENG | 2014-08-19 |
| 7890909 | Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow | Peter Lai, Ju H. Yew, Xi-An Xu, Xiaochun Gao | 2011-02-15 |
| 7484193 | Method and software for predicting the timing delay of a circuit path using two different timing models | Aveek Sarkar, Shian-Jiun Fu, Peter Lai | 2009-01-27 |
| 7036096 | Estimating capacitances using information including feature sizes extracted from a netlist | Aveek Sarkar, Yongning SHENG, Peter Lai | 2006-04-25 |
| 7007256 | Method and apparatus for power consumption analysis in global nets | Aveek Sarkar, Shyam Sundar, Peter Lai | 2006-02-28 |
| 6954914 | Method and apparatus for signal electromigration analysis | Shyam Sundar, Aveek Sarkar, Peter Lai, Teong Ming Cheah | 2005-10-11 |
| 6779131 | Reconfigurable multi-chip modules | Xuejun Yuan, Xiaowei Jin, Peter Lai, Samer H. Haddad, Jeffrey F. Wong | 2004-08-17 |
| 6596563 | Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug | Xuejun Yuan, Xiaowei Jin, Raymond A. Heald, James M. Kaku, Helen Dunn +3 more | 2003-07-22 |
| 6396149 | Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug | Xuejun Yuan, Xiaowei Jin, Raymond A. Heald, James M. Kaku, Helen Dunn +3 more | 2002-05-28 |