Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7890909 | Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow | Rambabu Pyapali, Ju H. Yew, Xi-An Xu, Xiaochun Gao | 2011-02-15 |
| 7484193 | Method and software for predicting the timing delay of a circuit path using two different timing models | Aveek Sarkar, Shian-Jiun Fu, Rambabu Pyapali | 2009-01-27 |
| 7284215 | Method to solve similar timing paths | Von-Kyoung Kim, Dakshesh Amin, Sriram Satakopan | 2007-10-16 |
| 7109757 | Leakage-tolerant dynamic wide-NOR circuit structure | Xeujun Yuan, Ye Xiong | 2006-09-19 |
| 7036096 | Estimating capacitances using information including feature sizes extracted from a netlist | Aveek Sarkar, Yongning SHENG, Rambabu Pyapali | 2006-04-25 |
| 7032200 | Low threshold voltage transistor displacement in a semiconductor device | Sriram Satakopan, Arvindvel Shanmugavel, Shunjiang Xu, Von-Kyoung Kim | 2006-04-18 |
| 7007256 | Method and apparatus for power consumption analysis in global nets | Aveek Sarkar, Shyam Sundar, Rambabu Pyapali | 2006-02-28 |
| 6954914 | Method and apparatus for signal electromigration analysis | Shyam Sundar, Aveek Sarkar, Rambabu Pyapali, Teong Ming Cheah | 2005-10-11 |
| 6779131 | Reconfigurable multi-chip modules | Rambabu Pyapali, Xuejun Yuan, Xiaowei Jin, Samer H. Haddad, Jeffrey F. Wong | 2004-08-17 |
| 6775813 | Aggregation of storage elements into stations and placement of same into an integrated circuit or design | Sachin Chopra, Yu-Yen Mo, Shyam Sundar, Kong-Fai Woo, Venkat R. Podduturi +1 more | 2004-08-10 |
| 6654942 | Method and system for providing a netlist driven integrated router in a non-netlist driven environment | Sachin Chopra, Peter Fu, Kong-Fal Woo, Srirarm Satakopan, Hsiu-Nien Chen +2 more | 2003-11-25 |
| 6596563 | Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug | Xuejun Yuan, Xiaowei Jin, Rambabu Pyapali, Raymond A. Heald, James M. Kaku +3 more | 2003-07-22 |
| 6396149 | Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug | Xuejun Yuan, Xiaowei Jin, Rambabu Pyapali, Raymond A. Heald, James M. Kaku +3 more | 2002-05-28 |