| 9348593 |
Instruction address encoding and decoding based on program construct groups |
Ramesh C. Tekumalla, Parag Madhani |
2016-05-24 |
| 8924801 |
At-speed scan testing of interface functional logic of an embedded memory or other circuit core |
Ramesh C. Tekumalla |
2014-12-30 |
| 8904255 |
Integrated circuit having clock gating circuitry responsive to scan shift control signal |
Ramesh C. Tekumalla |
2014-12-02 |
| 8799731 |
Clock control for reducing timing exceptions in scan testing of an integrated circuit |
Ramesh C. Tekumalla, Vijay Sharma |
2014-08-05 |
| 8793546 |
Integrated circuit comprising scan test circuitry with parallel reordered scan chains |
Ramesh C. Tekumalla, Parag Madhani |
2014-07-29 |
| 8726108 |
Scan test circuitry configured for bypassing selected segments of a multi-segment scan chain |
Ramesh C. Tekumalla, Niranjan Anant Pol, Vineet Sreekumar |
2014-05-13 |
| 8711013 |
Coding circuitry for difference-based data transformation |
Ramesh C. Tekumalla, Parag Madhani |
2014-04-29 |
| 8700962 |
Scan test circuitry configured to prevent capture of potentially non-deterministic values |
Ramesh C. Tekumalla |
2014-04-15 |
| 8677200 |
Integrated circuit with transition control circuitry for limiting scan test signal transitions during scan testing |
Ramesh C. Tekumalla |
2014-03-18 |
| 8645778 |
Scan test circuitry with delay defect bypass functionality |
Ramesh C. Tekumalla |
2014-02-04 |
| 8566658 |
Low-power and area-efficient scan cell for integrated circuit testing |
Ramesh C. Tekumalla, Priyesh Kumar, Parag Madhani |
2013-10-22 |
| 7711729 |
Searching a document based on a customer defined metadata schemata |
Lei Zhao, Richard Critchlow, Lijiang Fang |
2010-05-04 |
