Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10318691 | Timing analysis and optimization of asynchronous circuit designs | Roger David Carpenter | 2019-06-11 |
| 8893070 | Method for repeated block modification for chip routing | Jacob Avidan, Sandeep Grover, Roger David Carpenter | 2014-11-18 |
| 8407650 | Method for repeated block modification for chip routing | Jacob Avidan, Sandeep Grover, Roger David Carpenter | 2013-03-26 |