Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7424690 | Interconnect integrity verification | Richard T. Schultz, Robert D. Waldron, Larry Greenhouse | 2008-09-09 |
| 7082589 | Method of generating a schematic driven layout for a hierarchical integrated circuit design | Michael J. Saunders, C. Chip Brewster | 2006-07-25 |
| 6958541 | Low gate resistance layout procedure for RF transistor devices | Sean Erickson, Kevin Nunn | 2005-10-25 |