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Method for cycle accurate data transfer in a skewed synchronous clock domain |
Gyan Prakash |
2020-09-15 |
| 10725681 |
Method for calibrating the read latency of a DDR DRAM module |
Gyan Prakash, Chandrashekar Narla, Praphul Malige |
2020-07-28 |
| 10504569 |
System and method for controlling phase alignment of clock signals |
Gyan Prakash, Muniswara Reddy Vorugu |
2019-12-10 |
| 10312886 |
Asynchronous clock gating circuit |
Gyan Prakash |
2019-06-04 |
| 10297310 |
System and method for multi-cycle write leveling |
Gyan Prakash |
2019-05-21 |
| 9213359 |
Interface for controlling the phase alignment of clock signals for a recipient device |
Gyan Prakash |
2015-12-15 |
| 9105327 |
Memory controller using a data strobe signal and method of calibrating data strobe signal in a memory controller |
Gyan Prakash, Ranabir Dey |
2015-08-11 |
| 9042188 |
Memory controller and method of calibrating a memory controller |
Gyan Prakash |
2015-05-26 |
| 9007855 |
Data signal receiver and method of calibrating a data signal receiver |
Gyan Prakash, Muniswara Reddy Vorugu |
2015-04-14 |
| 8780655 |
Method and apparatus for aligning a clock signal and a data strobe signal in a memory system |
Gyan Prakash, Chandrashekar Narla |
2014-07-15 |
| 8773185 |
Calibration of delay chains |
Sivaramakrishnan Subramanian, Sridhar Cheruku |
2014-07-08 |
| 8502568 |
Receiver circuit with high input voltage protection |
Sandeep Dwivedi, Sridhar Cheruku |
2013-08-06 |
| 8427198 |
Reduced quantization error I/O resistor calibrator |
Sridhar Cheruku, Sivaramakrishnan Subramanian |
2013-04-23 |
| 8421516 |
Apparatus and method providing an interface between a first voltage domain and a second voltage domain |
Sridhar Cheruku, Manjunatha Prabhu |
2013-04-16 |
| 7986504 |
Distributing power to an integrated circuit |
Mikael Rien, Fabrice Blanc |
2011-07-26 |
| 7924056 |
Low voltage differential signalling driver |
Sandeep Dwivedi, Tippana Hari Babu |
2011-04-12 |