| 11935577 |
Physical interface and associated signal processing method for clock domain transfer of quarter-rate data |
Sivaramakrishnan Subramanian, Hussainvali Shaik, Ko-Ching Chao |
2024-03-19 |
| 11360709 |
Gate signal control circuit for DDR memory system |
Hong-Yi Wu, Sivaramakrishnan Subramanian, Ko-Ching Chao |
2022-06-14 |
| 11145343 |
Method for controlling multi-cycle write leveling process in memory system |
Sivaramakrishnan Subramanian, Hong-Yi Wu, Ko-Ching Chao |
2021-10-12 |
| 11005468 |
Duty-cycle correction circuit for DDR devices |
Sivaramakrishnan Subramanian, Sandeep Kumar Mohanta, Hussainvali Shaik |
2021-05-11 |
| 8773185 |
Calibration of delay chains |
Sivaramakrishnan Subramanian, Nidhir Kumar |
2014-07-08 |
| 8502568 |
Receiver circuit with high input voltage protection |
Sandeep Dwivedi, Nidhir Kumar |
2013-08-06 |
| 8427198 |
Reduced quantization error I/O resistor calibrator |
Sivaramakrishnan Subramanian, Nidhir Kumar |
2013-04-23 |
| 8421516 |
Apparatus and method providing an interface between a first voltage domain and a second voltage domain |
Nidhir Kumar, Manjunatha Prabhu |
2013-04-16 |