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Semiconductor memory devices including redundancy memory cells |
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Semiconductor memory devices including redundancy memory cells |
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Semiconductor memory devices and systems including data output circuits to output stored data during first output mode and output programmed data pattern during second output mode |
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Semiconductor memory device with a data output circuit configured to output stored data during a first type of read operation and configured to output at least one data pattern during a second type of read operation and methods thereof |
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Data output circuit and method in DDR synchronous semiconductor device |
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Semiconductor memory device with a data output circuit configured to output stored data during a first type of read operation and configured to output at least one data pattern during a second type of read operation and methods thereof |
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Data output circuit and method in DDR synchronous semiconductor device |
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Delay locked loop capable of compensating for delay of internal clock signal by variation of driving strength of output driver in semiconductor memory device |
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Circuit for generating a data strobe signal used in a double data rate synchronous semiconductor device |
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