Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11934219 | Integrated functional and design for testability (DFT) clock delivery architecture | Arvind Jain, Divya Gangadharan, Hong Dai, Madan Krishnappa | 2024-03-19 |
| 11005925 | Load balancing with power of random choices | Hiroshi Horii, Takayuki Osogami, Rudy Raymond Harry Putra | 2021-05-11 |