Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12164428 | System and method for event messages in a cache coherent interconnect | Michael Frank | 2024-12-10 |
| 12072805 | System and method to enter and exit a cache coherent interconnect | Michael Frank | 2024-08-27 |
| 11556477 | System and method for configurable cache IP with flushable address range | Jean-Philipe Loison | 2023-01-17 |
| 11489786 | Queue management system, starvation and latency management system, and methods of use | Michael Frank | 2022-11-01 |
| 11416352 | System and method for logic functional redundancy | Jean Philippe Loison, Benoit de LESCURE, Alexis Boutiller, Rohit Bansal, Parimal Gaikwad | 2022-08-16 |