| 12299449 |
Performance and power efficient processor when switching between fetching from decoded and non-decoded instruction sources |
John G. Favor |
2025-05-13 |
| 12282430 |
Macro-op cache data entry pointers distributed as initial pointers held in tag array and next pointers held in data array for efficient and performant variable length macro-op cache entries |
John G. Favor |
2025-04-22 |
| 12253951 |
Microprocessor with branch target buffer whose entries include fetch block hotness counters used for selective filtering of macro-op cache allocations |
John G. Favor |
2025-03-18 |
| 12118360 |
Branch target buffer miss handling |
John G. Favor |
2024-10-15 |
| 12106111 |
Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch address of a next fetch block |
John G. Favor |
2024-10-01 |
| 12020032 |
Prediction unit that provides a fetch block descriptor each clock cycle |
John G. Favor |
2024-06-25 |
| 12014180 |
Dynamically foldable and unfoldable instruction fetch pipeline |
John G. Favor, Vihar Soneji |
2024-06-18 |
| 12014178 |
Folded instruction fetch pipeline |
John G. Favor, Vihar Soneji |
2024-06-18 |
| 12008375 |
Branch target buffer that stores predicted set index and predicted way number of instruction cache |
John G. Favor, Vihar Soneji |
2024-06-11 |
| 11836498 |
Single cycle predictor |
John G. Favor |
2023-12-05 |
| 11816489 |
Microprocessor with prediction unit pipeline that provides a next fetch address at a rate of one per clock cycle |
John G. Favor |
2023-11-14 |