Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10620915 | Full adder circuits with reduced delay | Ying Wei, Jen-Hang Yang | 2020-04-14 |
| 10361686 | Scan output flip-flops | Wei-Min Hsu, Jen-Hang Yang | 2019-07-23 |
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10620915 | Full adder circuits with reduced delay | Ying Wei, Jen-Hang Yang | 2020-04-14 |
| 10361686 | Scan output flip-flops | Wei-Min Hsu, Jen-Hang Yang | 2019-07-23 |