Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406966 | Device with embedded high-bandwidth, high-capacity memory using wafer bonding | Khandker N. Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner +3 more | 2025-09-02 |
| 12105650 | Quasi-volatile system-level memory | Robert Norman, Eli Harari, Khandker N. Quader, Frank Sai-keung Lee, Richard S. Chernicoff +1 more | 2024-10-01 |
| 12068286 | Device with embedded high-bandwidth, high-capacity memory using wafer bonding | Khandker N. Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner +3 more | 2024-08-20 |
| 11923341 | Memory device including modular memory units and modular circuit units for concurrent memory operations | Khandker N. Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner +3 more | 2024-03-05 |
| 11670620 | Device with embedded high-bandwidth, high-capacity memory using wafer bonding | Khandker N. Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner +3 more | 2023-06-06 |
| 11580038 | Quasi-volatile system-level memory | Robert Norman, Eli Harari, Khandker N. Quader, Frank Sai-keung Lee, Richard S. Chernicoff +1 more | 2023-02-14 |
| 7890694 | Latched address multi-chunk write to EEPROM | Douglas J. Lee, Sanjay Mehrotra, Raul-Adrian Cernea | 2011-02-15 |
| 7532514 | Non-volatile memory and method with bit line to bit line coupled compensation | Raul-Adrian Cernea, Yan Li, Shahzad Khalid | 2009-05-12 |
| 7447093 | Method for controlling voltage in non-volatile memory systems | Jun Li, Prajit Nandi | 2008-11-04 |
| 7403434 | System for controlling voltage in non-volatile memory systems | Jun Li, Prajit Nandi | 2008-07-22 |
| 7269069 | Non-volatile memory and method with bit line to bit line coupled compensation | Raul-Adrian Cernea, Yan Li, Shahzad Khalid | 2007-09-11 |
| 7215574 | Non-volatile memory and method with bit line compensation dependent on neighboring operating modes | Shahzad Khalid, Yan Li, Raul-Adrian Cernea | 2007-05-08 |
| 7064980 | Non-volatile memory and method with bit line coupled compensation | Raul-Adrian Cernea, Yan Li, Shahzad Khalid | 2006-06-20 |
| 6956770 | Non-volatile memory and method with bit line compensation dependent on neighboring operating modes | Shahzad Khalid, Yan Li, Raul-Adrian Cernea | 2005-10-18 |
| 6829673 | Latched address multi-chunk write to EEPROM | Douglas J. Lee, Sanjay Mehrotra, Raul-Adrian Cernea | 2004-12-07 |
| 6542956 | Latched address multi-chunk write to EEPROM | Douglas J. Lee, Sanjay Mehrotra, Raul-Adrian Cernea | 2003-04-01 |
| 6157983 | Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM | Douglas J. Lee, Sanjay Mehrotra, Raul-Adrian Cernea | 2000-12-05 |
| 6069039 | Plane decode/virtual sector architecture | Douglas J. Lee, Sanjay Mehrotra, Daniel C. Guterman | 2000-05-30 |
| 5890192 | Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM | Douglas J. Lee, Sanjay Mehrotra, Raul-Adrian Cernea | 1999-03-30 |
| 5798968 | Plane decode/virtual sector architecture | Douglas J. Lee, Sanjay Mehrotra, Daniel C. Guterman | 1998-08-25 |
| 5693570 | Process for manufacturing a programmable power generation circuit for flash EEPROM memory systems | Raul-Ardian Cernea, Douglas J. Lee, Sanjay Mehrotra | 1997-12-02 |
| 5621685 | Programmable power generation circuit for flash EEPROM memory systems | Raul-Adrian Cernea, Douglas J. Lee, Sanjay Mehrotra | 1997-04-15 |
| 5596532 | Flash EEPROM self-adaptive voltage generation circuit operative within a continuous voltage source range | Raul-Adrian Cernea, Douglas J. Lee, Sanjay Mehrotra | 1997-01-21 |
| 5592420 | Programmable power generation circuit for flash EEPROM memory systems | Raul-Adrian Cernea, Douglas J. Lee, Sanjay Mehrotra | 1997-01-07 |
| 5568424 | Programmable power generation circuit for flash EEPROM memory systems | Raul-Adrian Cernea, Douglas J. Lee, Sanjay Mehrotra | 1996-10-22 |