Issued Patents All Time
Showing 25 most recent of 103 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12211549 | Cell cycling to minimize resistive memory random number correlation | Sung Hyun Jo | 2025-01-28 |
| 12119058 | Error correction for identifier data generated from unclonable characteristics of resistive memory | — | 2024-10-15 |
| 12087397 | Dynamic host allocation of physical unclonable feature operation for resistive switching memory | — | 2024-09-10 |
| 11923005 | Cell cycling to minimize resistive memory random number correlation | Sung Hyun Jo | 2024-03-05 |
| 11823739 | Physically unclonable function (PUF) generation involving high side programming of bits | Sung Hyun Jo | 2023-11-21 |
| 11727986 | Physically unclonable function (PUF) generation involving programming of marginal bits | Sung Hyun Jo | 2023-08-15 |
| 11270767 | Non-volatile memory bank with embedded inline computing logic | — | 2022-03-08 |
| 11270769 | Network router device with hardware-implemented lookups including two-terminal non-volatile memory | Hagop Nazarian | 2022-03-08 |
| 11222696 | Computing memory architecture | Hagop Nazarian, Christophe Sucur, Sylvain Dubois | 2022-01-11 |
| 11127460 | Resistive random access memory matrix multiplication structures and methods | Hagop Nazarian, Christophe Sucur, Sylvain Dubois | 2021-09-21 |
| 11126550 | Integrating a resistive memory system into a multicore CPU die to achieve massive memory parallelism | Donald Yeung, Bruce Ledley Jacob, Sylvain Dubois | 2021-09-21 |
| 10949091 | Memory controllers, memory systems, solid state drives and methods for processing a number of commands | Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie | 2021-03-16 |
| 10749529 | Memory device including integrated deterministic pattern recognition circuitry | — | 2020-08-18 |
| 10699785 | Computing memory architecture | Hagop Nazarian, Christophe Sucur, Sylvain Dubois | 2020-06-30 |
| 10592429 | Cache management for memory module comprising two-terminal resistive memory | Robin Sarno, Ruchirkumar D. Shah | 2020-03-17 |
| 10489700 | Neuromorphic logic for an array of high on/off ratio non-volatile memory cells | Tanmay Kumar, Hagop Nazarian, Sung Hyun Jo | 2019-11-26 |
| 10409714 | Logical to physical translation for two-terminal memory | Ruchirkumar D. Shah | 2019-09-10 |
| 10388374 | Programmable logic applications for an array of high on/off ratio and high speed non-volatile memory cells | Hagop Nazarian, Lin-Shih Liu | 2019-08-20 |
| 10347335 | Node retainer circuit incorporating RRAM | Hagop Nazarian | 2019-07-09 |
| 10331351 | Memory controllers, memory systems, solid state drives and methods for processing a number of commands | Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie | 2019-06-25 |
| 10248333 | Write distribution techniques for two-terminal memory wear leveling | Ruchirkumar D. Shah | 2019-04-02 |
| 10169128 | Reduced write status error polling for non-volatile resistive memory device | Robin Sarno, Ruchirkumar D. Shah | 2019-01-01 |
| 10101924 | Storage processor managing NVMe logically addressed solid state disk array | Siamack Nemazie | 2018-10-16 |
| 10056907 | Field programmable gate array utilizing two-terminal non-volatile memory | Hagop Nazarian, Sang Thanh Nguyen | 2018-08-21 |
| 10050629 | Multi-buffered shift register input matrix to FPGA | Hagop Nazarian | 2018-08-14 |