Issued Patents All Time
Showing 25 most recent of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7223688 | Single level metal memory cell using chalcogenide cladding | Tyler Lowrey | 2007-05-29 |
| 7157304 | Single level metal memory cell using chalcogenide cladding | Tyler Lowrey | 2007-01-02 |
| 6995446 | Isolating phase change memories with schottky diodes and guard rings | Ilya V. Karpov | 2006-02-07 |
| 6912146 | Using an MOS select gate for a phase change memory | Tyler Lowrey | 2005-06-28 |
| 6836423 | Single level metal memory cell using chalcogenide cladding | Tyler Lowrey | 2004-12-28 |
| 6791107 | Silicon on insulator phase change memory | Tyler Lowrey | 2004-09-14 |
| 6625054 | Method and apparatus to program a phase change memory | Tyler Lowrey | 2003-09-23 |
| 6567293 | Single level metal memory cell using chalcogenide cladding | Tyler Lowrey | 2003-05-20 |
| 6545907 | Technique and apparatus for performing write operations to a phase change material memory device | Tyler Lowrey, Ward Parkinson | 2003-04-08 |
| 6531373 | Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements | Tyler Lowrey | 2003-03-11 |
| 5740105 | Memory cell array with LOCOS free isolation | — | 1998-04-14 |
| 5661060 | Method for forming field oxide regions | Etan Shacham | 1997-08-26 |
| 5570314 | EEPROM devices with smaller cell size | — | 1996-10-29 |
| RE35356 | EEPROM cell array with tight erase distribution | — | 1996-10-22 |
| 5565371 | Method of making EPROM with separate erasing and programming regions | — | 1996-10-15 |
| 5550772 | Memory array utilizing multi-state memory cells | — | 1996-08-27 |
| 5537362 | Low-voltage EEPROM using charge-pumped word lines | Vincent L. Fong | 1996-07-16 |
| 5523249 | Method of making an EEPROM cell with separate erasing and programming regions | David J. McElroy, Sung-Wei Lin, Inn K. Lee | 1996-06-04 |
| 5521110 | Method of making EEPROM devices with smaller cell size | — | 1996-05-28 |
| 5469383 | Memory cell array having continuous-strip field-oxide regions | Dave J. McElroy, Pradeep L. Shah | 1995-11-21 |
| 5420060 | Method of making contract-free floating-gate memory array with silicided buried bitlines and with single-step defined floating gates | Howard L. Tigelaar | 1995-05-30 |
| 5418741 | Virtual ground memory cell array | — | 1995-05-23 |
| 5371031 | Method of making EEPROM array with buried N+ windows and with separate erasing and programming regions | Inn K. Lee | 1994-12-06 |
| 5365082 | MOSFET cell array | Pradeep L. Shah, Dave J. McElroy | 1994-11-15 |
| 5354703 | EEPROM cell array with tight erase distribution | — | 1994-10-11 |