Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10198545 | Systems and methods for extraction of electrical specifications from prelayout simulations | Tat Hin Tan, Chieu Fung Tan, My Chien Yee | 2019-02-05 |
| 8276104 | Stress reduction on vias and yield improvement in layout design through auto generation of via fill | Gregory Sylvester Emmanuel, Hui-Peng Ong, Joseph Lin | 2012-09-25 |