Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12160256 | DAC-based transmit driver architecture with improved bandwidth | Chi Fung Poon, Chuen Chou, Weerachai Neeranartvong | 2024-12-03 |
| 11984817 | Low power inverter-based CTLE | Junho Cho, Parag Upadhyaya | 2024-05-14 |
| 11894959 | Ultra-high-speed PAM-N CMOS inverter serial link | Ronan Casey, Lokesh Rajendran, Declan Carey, Catherine Hearne, Hongtao Zhang | 2024-02-06 |
| 11764797 | Offset mitigation for an analog-to-digital convertor | Kai-An Hsieh, Tan Kee Hian | 2023-09-19 |
| 11728962 | Multi-phase clock signal generation circuitry | Shaojun MA, Chi Fung Poon, Parag Upadhyaya | 2023-08-15 |
| 11522735 | Digital noise-shaping FFE/DFE for ADC-based wireline links | Hongtao Zhang, Geoffrey Zhang | 2022-12-06 |
| 11489705 | Integrated circuit including a continuous time linear equalizer (CTLE) circuit and method of operation | Ronan Casey, Catherine Hearne | 2022-11-01 |
| 11398934 | Ultra-high-speed PAM-N CMOS inverter serial link | Ronan Casey, Lokesh Rajendran, Declan Carey, Catherine Hearne, Hongtao Zhang | 2022-07-26 |
| 11190199 | Asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) timing adjustment based on output statistics | David A. Freitas, Hsung Jai Im | 2021-11-30 |
| 11177984 | CMOS analog circuits having a triode-based active load | Chuen Chou, Hsung Jai Im | 2021-11-16 |
| 11133963 | Dsp cancellation of track-and-hold induced ISI in ADC-based serial links | Ronan Casey | 2021-09-28 |
| 10998307 | CMOS analog circuits having a triode-based active load | Chuen Chou, Hsung Jai Im | 2021-05-04 |
| 10469090 | Inverter-based filter biasing with ring oscillator-based supply regulation | — | 2019-11-05 |
| 10050814 | CTLE gear shifting to enable CDR frequency lock in wired communication | Reza Hoshyar, Nirmal C. Warke, Wenting Zhou, Ali Kiaei, Ahmad Bahai | 2018-08-14 |
| 9917663 | Apparatus, system, and method for configuring a serializer/deserializer based on evaluation of a probe signal | Hiroshi Takatori, Zhan Duan | 2018-03-13 |
| 9614659 | CTLE gear shifting to enable CDR frequency lock in wired communication | Reza Hoshyar, Nirmal C. Warke, Wenting Zhou, Ali Kiaei, Ahmad Bahai | 2017-04-04 |
| 9479366 | IIR DFE updating gain and time constants using LMS equations | Reza Hoshyar, Nirmal C. Warke, Ali Kiaei, Ahmad Bahai | 2016-10-25 |
| 9397824 | Gear shifting from binary phase detector to PAM phase detector in CDR architecture | Reza Hoshyar, Nirmal C. Warke, Ali Kiaei, Ahmad Bahai | 2016-07-19 |