Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12124391 | Semi-programmable and reconfigurable co-accelerator for a deep neural network with normalization or non-linearity | Stephen Sangho Youn, Steven K. Reinhardt, Jeremy Fowers, Lok Chand Koppaka | 2024-10-22 |
| 11790212 | Quantization-aware neural architecture search | Eric S. Chung, Vahideh Akhlaghi, Ritchie Zhao | 2023-10-17 |
| 11734214 | Semi-programmable and reconfigurable co-accelerator for a deep neural network with normalization or non-linearity | Stephen Sangho Youn, Steven K. Reinhardt, Jeremy Fowers, Lok Chand Koppaka | 2023-08-22 |
| 11604960 | Differential bit width neural architecture search | Eric S. Chung, Vahideh Akhlaghi, Ritchie Zhao | 2023-03-14 |
| 11556762 | Neural network processor based on application specific synthesis specialization parameters | Jeremy Fowers, Eric S. Chung, Todd Michael Massengill, Ming Liu, Gabriel Leonard Weisz | 2023-01-17 |
| 11200486 | Convolutional neural networks on hardware accelerators | Eric S. Chung, Karin Strauss, Joo Young Kim, Olatunji Ruwase | 2021-12-14 |
| 11157801 | Neural network processing with the neural network model pinned to on-chip memories of hardware nodes | Eric S. Chung, Douglas C. Burger, Jeremy Fowers | 2021-10-26 |
| 10795678 | Matrix vector multiplier with a vector register file comprising a multi-port memory | Jeremy Fowers, Eric S. Chung, Todd Michael Massengill, Ming Liu, Gabriel Leonard Weisz | 2020-10-06 |
| 10566076 | Customized integrated circuit for serial comparison of nucleotide sequences | Daniel Lo, Eric S. Chung, Ravindra Pandya, David E. Heckerman | 2020-02-18 |
| 10452971 | Deep neural network partitioning on servers | Eric S. Chung, Karin Strauss, Joo Young Kim, Olatunji Ruwase | 2019-10-22 |
| 10372456 | Tensor processor instruction set architecture | Jeremy Fowers, Steven K. Reinhardt, Eric S. Chung, Ming Liu | 2019-08-06 |
| 10338925 | Tensor register files | Jeremy Fowers, Steven K. Reinhardt, Eric S. Chung | 2019-07-02 |
| 10331445 | Multifunction vector processor circuits | Jeremy Fowers, Ming Liu, Steven K. Reinhardt, Eric S. Chung | 2019-06-25 |
| 10241970 | Reduced memory nucleotide sequence comparison | Daniel Lo, Eric S. Chung, Ravindra Pandya, David E. Heckerman, Roman Snytsar | 2019-03-26 |
| 10167800 | Hardware node having a matrix vector unit with block-floating point processing | Eric S. Chung, Douglas C. Burger, Daniel Lo | 2019-01-01 |
| 9367519 | Sparse matrix data structure | Karin Strauss, Jeremy Fowers | 2016-06-14 |