Issued Patents All Time
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11676650 | Apparatuses and methods for deactivating a delay locked loop update in semiconductor devices | Yasuo Satoh, Kenji Mae | 2023-06-13 |
| 11594265 | Apparatus including parallel pipeline control and methods of manufacturing the same | Navya Sri Sreeram, Kallol Mazumder, Ryo Fujimaki, Yutaka Uemura | 2023-02-28 |
| 11348633 | Selectively controlling clock transmission to a data (DQ) system | — | 2022-05-31 |
| 11087806 | Apparatuses and methods for adjusting delay of command signal path | Atsuko Momma | 2021-08-10 |
| 11049543 | Apparatuses and methods for deactivating a delay locked loop update in semiconductor devices | Yasuo Satoh, Kenji Mae | 2021-06-29 |
| 10931270 | Apparatuses and methods for data transmission offset values in burst transmissions | Yasuo Satoh | 2021-02-23 |
| 10924097 | Shifter circuits having registers arranged in a folded topology | — | 2021-02-16 |
| 10892002 | Selectively controlling clock transmission to a data (DQ) system | — | 2021-01-12 |
| 10755758 | Methods and apparatuses including command delay adjustment circuit | Shuichi Ishibashi, Hiroki Fujisawa | 2020-08-25 |
| 10636463 | Techniques for command synchronization in a memory device | Yoshiya Komatsu, Atsuko Momma | 2020-04-28 |
| 10608620 | Shifter circuits having registers arranged in a folded topology | — | 2020-03-31 |
| 10516391 | Apparatuses and methods for data transmission offset values in burst transmissions | Yasuo Satoh | 2019-12-24 |
| 10403340 | Techniques for command synchronization in a memory device | Yoshiya Komatsu, Atsuko Momma | 2019-09-03 |
| 10290336 | Methods and apparatuses including command delay adjustment circuit | Shuichi Ishibashi, Hiroki Fujisawa | 2019-05-14 |
| 9997220 | Apparatuses and methods for adjusting delay of command signal path | Atsuko Momma | 2018-06-12 |
| 9865317 | Methods and apparatuses including command delay adjustment circuit | Shuichi Ishibashi, Hiroki Fujisawa | 2018-01-09 |
| 9570149 | Output signal generation device having a phase adjustment unit and method for adjusting a phase difference between an input and an output signal | — | 2017-02-14 |
| 9531363 | Methods and apparatuses including command latency control circuit | — | 2016-12-27 |
| 9438251 | Clock generating circuit, semiconductor device including the same, and data processing system | — | 2016-09-06 |
| 9196349 | Semiconductor device | Hiroki Fujisawa | 2015-11-24 |
| 9053779 | Semiconductor device | Ryuji Takishita, Takeshi Konno | 2015-06-09 |
| 9007861 | Clock generating circuit, semiconductor device including the same, and data processing system | — | 2015-04-14 |
| 8917563 | Semiconductor device and information processing system including an input circuit with a delay | Hiroyuki Inage | 2014-12-23 |
| 8732512 | Semiconductor device having DLL circuit | — | 2014-05-20 |
| 8564361 | Semiconductor device and method of controlling the same | Hitoshi Tanaka | 2013-10-22 |