Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12191866 | Linear prediction to suppress spurs in a digital phase-locked loop | — | 2025-01-07 |
| 12166494 | Modified control loop in a digital phase-locked loop | — | 2024-12-10 |
| 11764913 | Jitter self-test using timestamps | Raghunandan K. Ranganathan, Srisai R. Seethamraju | 2023-09-19 |
| 11228403 | Jitter self-test using timestamps | Raghunandan K. Ranganathan, Srisai R. Seethamraju | 2022-01-18 |
| 11018679 | On-chip phase-locked loop response measurement | — | 2021-05-25 |
| 10819354 | Accurate and reliable digital PLL lock indicator | James D. Barnette | 2020-10-27 |
| 10608649 | Relative frequency offset error and phase error detection for clocks | James D. Barnette | 2020-03-31 |