| 8341499 |
System and method for error detection in a redundant memory system |
— |
2012-12-25 |
| 8321758 |
Data error correction device and methods thereof |
— |
2012-11-27 |
| 7415551 |
Multi-host virtual bridge input-output resource switch |
— |
2008-08-19 |
| 6321296 |
SDRAM L3 cache using speculative loads with command aborts to lower latency |
— |
2001-11-20 |
| 5809537 |
Method and system for simultaneous processing of snoop and cache operations |
Randall C. Itskin, Amjad Qureshi, David Brian Ruth |
1998-09-15 |
| 5754865 |
Logical address bus architecture for multiple processor systems |
Randall C. Itskin, David Brian Ruth |
1998-05-19 |
| 5604754 |
Validating the synchronization of lock step operated circuits |
Randall C. Itskin, David Brian Ruth |
1997-02-18 |
| 4870566 |
Scannerless message concentrator and communications multiplexer |
Ronald J. Cooper, Mario A. Marsico, Richard Colbert Matlack, Jr., Robert L. Smith |
1989-09-26 |
| 4837677 |
Multiple port service expansion adapter for a communications controller |
Gilbert S. Burrus, Jr., Ronald J. Cooper, Michael R. Marr, Mario A. Marsico, Paul D. Sullivan |
1989-06-06 |
| 4751634 |
Multiple port communications adapter apparatus |
Gilbert S. Burrus, Jr., Ronald J. Cooper, Michael R. Marr, Mario A. Marsico, Paul D. Sullivan |
1988-06-14 |
| 4716523 |
Multiple port integrated DMA and interrupt controller and arbitrator |
Gilbert S. Burrus, Jr., Ronald J. Cooper, Michael R. Marr, Mario A. Marsico |
1987-12-29 |
| 4648029 |
Multiplexed interrupt/DMA request arbitration apparatus and method |
Ronald J. Cooper, Mario A. Marsico, Paul D. Sullivan |
1987-03-03 |
| 4627054 |
Multiprocessor array error detection and recovery apparatus |
Ronald J. Cooper, Mario A. Marsico |
1986-12-02 |
