Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7519927 | Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations | Heidi L. Lagares-Vazquez, Ray Raphy, Alan Daniel Stigliani, Charles Vakirtzis | 2009-04-14 |
| 4709166 | Complementary cascoded logic circuit | Dennis C. Banker, Jack A. Dorler | 1987-11-24 |