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Programmable on-chip logic analyzer apparatus, systems, and methods |
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Programmable on-chip logic analyzer apparatus, systems, and methods |
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Providing memory test patterns for DLL calibration |
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System and method for dynamic buffer allocation |
— |
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Dynamic buffer allocation for a computer system |
— |
2003-07-29 |
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Apparatus for flexibly allocating request/grant pins between multiple bus controllers |
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2002-05-14 |
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Method for flexibly allocating request/grant pins between multiple bus controllers |
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2002-05-07 |
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Dynamic buffer allocation for a computer system |
— |
2001-06-05 |
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System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair |
— |
2000-06-06 |
| 5857095 |
Method for aligning a control signal and a clock signal |
Joseph M. Jeddeloh, Richard F. Nicholson, Dean A. Klein |
1999-01-05 |
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Memory controller with low skew control signal |
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| 5692165 |
Memory controller with low skew control signal |
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1997-11-25 |
