| 12307355 |
Neural network processing with chained instructions |
Eric S. Chung, Douglas C. Burger |
2025-05-20 |
| 12124391 |
Semi-programmable and reconfigurable co-accelerator for a deep neural network with normalization or non-linearity |
Stephen Sangho Youn, Steven K. Reinhardt, Lok Chand Koppaka, Kalin Ovtcharov |
2024-10-22 |
| 11886833 |
Hierarchical and shared exponent floating point data types |
Bita Darvish Rouhani, Venmugil Elango, Rasoul SHAFIPOUR, Ming Liu, Jinwen Xi +2 more |
2024-01-30 |
| 11734214 |
Semi-programmable and reconfigurable co-accelerator for a deep neural network with normalization or non-linearity |
Stephen Sangho Youn, Steven K. Reinhardt, Lok Chand Koppaka, Kalin Ovtcharov |
2023-08-22 |
| 11663450 |
Neural network processing with chained instructions |
Eric S. Chung, Douglas C. Burger |
2023-05-30 |
| 11556764 |
Deriving a concordant software neural network layer from a quantized firmware neural network layer |
Daniel Lo, Deeksha Dangwal |
2023-01-17 |
| 11556762 |
Neural network processor based on application specific synthesis specialization parameters |
Kalin Ovtcharov, Eric S. Chung, Todd Michael Massengill, Ming Liu, Gabriel Leonard Weisz |
2023-01-17 |
| 11243778 |
Instruction dispatch for superscalar processors |
Skand HURKAT |
2022-02-08 |
| 11157801 |
Neural network processing with the neural network model pinned to on-chip memories of hardware nodes |
Eric S. Chung, Douglas C. Burger, Kalin Ovtcharov |
2021-10-26 |
| 11151445 |
Neural network processor with a window expander circuit |
Dan Zhang, Mohammadmahdi Ghandi |
2021-10-19 |
| 11144820 |
Hardware node with position-dependent memories for neural network processing |
Eric S. Chung, Douglas C. Burger |
2021-10-12 |
| 11132599 |
Multi-function unit for programmable hardware nodes for neural network processing |
Eric S. Chung, Douglas C. Burger |
2021-09-28 |
| 10795678 |
Matrix vector multiplier with a vector register file comprising a multi-port memory |
Kalin Ovtcharov, Eric S. Chung, Todd Michael Massengill, Ming Liu, Gabriel Leonard Weisz |
2020-10-06 |
| 10467324 |
Data packing techniques for hard-wired multiplier circuits |
Eric S. Chung, Shlomo Alkalay |
2019-11-05 |
| 10372456 |
Tensor processor instruction set architecture |
Kalin Ovtcharov, Steven K. Reinhardt, Eric S. Chung, Ming Liu |
2019-08-06 |
| 10338925 |
Tensor register files |
Steven K. Reinhardt, Kalin Ovtcharov, Eric S. Chung |
2019-07-02 |
| 10331445 |
Multifunction vector processor circuits |
Ming Liu, Kalin Ovtcharov, Steven K. Reinhardt, Eric S. Chung |
2019-06-25 |
| 10140252 |
Hardware node with matrix-vector multiply tiles for neural network processing |
Eric S. Chung |
2018-11-27 |
| 9590655 |
Scalable high-bandwidth architecture for lossless compression |
Joo Young Kim, Douglas C. Burger, Scott A. Hauck |
2017-03-07 |
| 9367519 |
Sparse matrix data structure |
Karin Strauss, Kalin Ovtcharov |
2016-06-14 |
