Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10439620 | Dual-PFD feedback delay generation circuit | Theertham Srinivas, Peeyoosh Mirajkar | 2019-10-08 |
| 10243573 | Phase syncronizing PLL output across reference and VCO clock domains | Peeyoosh Mirajkar, Shankaranarayana Karantha, Ashwin Ravisankar, Srikanth Manian, Srinivas Theertham | 2019-03-26 |
| 9954705 | Phase noise improvement techniques for wideband fractional-N synthesizers | Yogesh Darwhekar, Srikanth Manian, Srinivas Theertham, Robert Karl Butler | 2018-04-24 |
| 9948312 | Phase lock loop with a digital charge pump | Jayawardan Janardhanan, Krishnaswamy Thiagarajan | 2018-04-17 |
| 9667300 | Frequency synthesizer for achieving fast re-lock between alternate frequencies in low bandwidth PLLs | Krishnaswamy Thiagarajan, Jayawardan Janardhanan, Srikanth Manian | 2017-05-30 |
| 9509323 | Fractional-N synthesizer with pre-multiplication | Krishnaswamy Thiagarajan, Srikanth Manian, Debapriya Sahu | 2016-11-29 |
| 9503105 | Phase frequency detector (PFD) circuit with improved lock time | Peeyoosh Mirajkar, Sankaran Aniruddhan | 2016-11-22 |
| 9407249 | System and method for pulse width modulation | Sumantra Seth, Uttam Kumar Patro, Biman Chattopadhyay | 2016-08-02 |
| 9407424 | Fast locking clock and data recovery using only two samples per period | Bharathi Rahuldev Holla, Biman Chattopadhyay, Sujoy Chakravarty, Sumantra Seth | 2016-08-02 |
| 8742823 | Driver output pad leakage current compensation | Sumantra Seth | 2014-06-03 |
| 7965100 | Transmitter with internal compensation for variance in differential data line impedance | Peter Brendan Considine, Olivier Stéphane Simon Depuits | 2011-06-21 |