Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7685455 | Semiconductor integrated circuit which generates internal clock signal for fetching input data synchronously with the internal clock signal without decrease of timing margin | Masao Shinozaki, Kazuo Kanetani, Hideto Kazama | 2010-03-23 |
| 7426152 | Semiconductor memory device and semiconductor device | Masahiro Yamashita, Takashi Uehara, Mamoru Takaku | 2008-09-16 |
| 7296173 | Semiconductor integrated circuit | Masao Shinozaki, Kazuo Kanetani, Hideto Kazama | 2007-11-13 |
| 7269086 | Semiconductor memory device and semiconductor device | Masahiro Yamashita, Takashi Uehara, Mamoru Takaku | 2007-09-11 |
| 7233045 | Semiconductor device and system | Takemi Negishi, Kazuo Kanetani, Hideto Kazama | 2007-06-19 |
| 7164592 | Semiconductor device | Yasuhiro Yoshikawa, Motoo Suwa | 2007-01-16 |
| 7123534 | Semiconductor memory device having short refresh time | Noriyuki Homma | 2006-10-17 |
| 6998878 | Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit | Kazuo Kanetani, Kaname Yamasaki, Takeshi Kusunoki, Keiichi Higeta, Kunihiko Yamaguchi +1 more | 2006-02-14 |
| 6954401 | Semiconductor memory device integrating source-coupled-logic (SCL) circuit into an address buffer and a decoder | Kazuo Kanetani | 2005-10-11 |
| 6876573 | Semiconductor memory device | Keiichi Higeta, Shigeru Nakahara | 2005-04-05 |
| 6842394 | Semiconductor device using SCL circuit | Kazuo Kanetani | 2005-01-11 |
| 6807115 | Method of testing a semiconductor integrated device | Kazuo Kanetani, Kaname Yamasaki, Fumihiko Arakawa, Takeshi Kusunoki, Keiichi Higeta | 2004-10-19 |
| 6806516 | Semiconductor device and system | Takemi Negishi, Kazuo Kanetani, Hideto Kazama | 2004-10-19 |
| 6791895 | Semiconductor memory device | Keiichi Higeta, Shigeru Nakahara | 2004-09-14 |
| 6677782 | Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit | Kazuo Kanetani, Kaname Yamasaki, Takeshi Kusunoki, Keiichi Higeta, Kunihiko Yamaguchi +1 more | 2004-01-13 |
| 6657887 | Semiconductor memory device having improved noise margin, faster read rate and reduced power consumption | Keiichi Higeta, Shigeru Nakahara | 2003-12-02 |
| 6617610 | Semiconductor integrated circuit | Kazuo Kanetani, Kaname Yamasaki, Fumihiko Arakawa, Takeshi Kusunoki, Keiichi Higeta | 2003-09-09 |
| 6476644 | Clocked logic gate circuit | Kazuo Kanetani, Kaname Yamasaki, Noboru Masuda, Kenji Kaneko, Makoto Hanawa +1 more | 2002-11-05 |
| 6438050 | Signal transmission circuit and semiconductor memory using the same | Kazuo Kanetani, Kaname Yamasaki, Takeshi Kusunoki, Fumihiko Arakawa | 2002-08-20 |
| 6369617 | Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit | Kazuo Kanetani, Kaname Yamasaki, Takeshi Kusunoki, Keiichi Higeta, Kunihiko Yamaguchi +1 more | 2002-04-09 |
| 6356493 | Signal transmission circuit and semiconductor memory using the same | Kazuo Kanetani, Kaname Yamasaki, Takeshi Kusunoki, Fumihiko Arakawa | 2002-03-12 |
| 6337581 | Signal transmission circuit and semiconductor memory using the same | Kazuo Kanetani, Kaname Yamasaki, Takeshi Kusunoki, Fumihiko Arakawa | 2002-01-08 |
| 6333645 | Clocked logic gate circuit | Kazuo Kanetani, Kaname Yamasaki, Noboru Masuda, Kenji Kaneko, Makoto Hanawa +1 more | 2001-12-25 |
| 6333881 | Semiconductor memory | Takeshi Kusunoki, Fumihiko Arakawa, Kazuo Kanetani, Kaname Yamasaki | 2001-12-25 |
| 6316961 | Clocked logic gate circuit | Kazuo Kanetani, Kaname Yamasaki, Noboru Masuda, Kenji Kaneko, Makoto Hanawa +1 more | 2001-11-13 |