Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8336007 | Verifiable multimode multipliers | — | 2012-12-18 |
| 8095899 | Verifiable multimode multipliers | — | 2012-01-10 |
| 7506017 | Verifiable multimode multipliers | — | 2009-03-17 |
| 7308659 | Apparatus and method for RTL modeling of a register | Gopinath Rangan, Wira Gunawan, Tzung-Chin Chang, Khai Nguyen | 2007-12-11 |
| 7178117 | Apparatus and method for RTL based full chip modeling of a programmable logic device | Zunghang Yu, Ninh D. Ngo | 2007-02-13 |
| 6836877 | Automatic synthesis script generation for synopsys design compiler | — | 2004-12-28 |
| 6421818 | Efficient top-down characterization method | Kevin C. Cleereman | 2002-07-16 |
| 6378123 | Method of handling macro components in circuit design synthesis | — | 2002-04-23 |
| 6295636 | RTL analysis for improved logic synthesis | — | 2001-09-25 |
| 6292931 | RTL analysis tool | — | 2001-09-18 |
| 6289491 | Netlist analysis tool by degree of conformity | — | 2001-09-11 |
| 6289498 | VDHL/Verilog expertise and gate synthesis automation system | — | 2001-09-11 |
| 6263483 | Method of accessing the generic netlist created by synopsys design compilier | — | 2001-07-17 |
| 6205572 | Buffering tree analysis in mapped design | — | 2001-03-20 |
| 6173435 | Internal clock handling in synthesis script | — | 2001-01-09 |