Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7304969 | Automatic gain control and low power start-of-packet detection for a wireless LAN receiver | Philip J. Ryan, Andrew R. Adams, John D. O'Sullivan, Uri Parker, Brian D. Hart | 2007-12-04 |
| 7151759 | Automatic gain control and low power start-of-packet detection for a wireless LAN receiver | Philip J. Ryan, Andrew R. Adams, John D. O'Sullivan, Uri Parker, Brian Hart | 2006-12-19 |
| 6031992 | Combining hardware and software to provide an improved microprocessor | Robert F. Cmelik, David R. Ditzel, Edmund J. Kelly, Colin B. Hunter, Douglas A. Laird +1 more | 2000-02-29 |
| 5870323 | Three overlapped stages of radix-2 square root/division with speculative execution | J. Arjun Prabhu | 1999-02-09 |
| 5787030 | Correct and efficient sticky bit calculation for exact floating point divide/square root results | J. Arjun Prabhu | 1998-07-28 |
| 5696712 | Three overlapped stages of radix-2 square root/division with speculative execution | J. Arjun Prabhu | 1997-12-09 |
| 5671171 | Shared rounding hardware for multiplier and divider/square root unit using conditional sum adder | Robert K. Yu | 1997-09-23 |
| 5619439 | Shared hardware for multiply, divide, and square root exponent calculation | Robert K. Yu | 1997-04-08 |
| 5602769 | Method and apparatus for partially supporting subnormal operands in floating point multiplication | Robert K. Yu | 1997-02-11 |
| 5150319 | Circuitry for rounding in a floating point multiplier | — | 1992-09-22 |
| 5072419 | Binary tree multiplier constructed of carry save adders having an area efficient floor plan | — | 1991-12-10 |