Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12170100 | Systems for and methods for fast mode hop detection and correction for hard disk drive recording systems | Scott O'Brien | 2024-12-17 |
| 9490812 | Configurable clock network for programmable logic device | Kang Wei Lai, Richard Yen-Hsiang Chang | 2016-11-08 |
| 8680913 | Configurable clock network for programmable logic device | Kang Wei Lai, Richard Yen-Hsiang Chang | 2014-03-25 |
| 8441314 | Configurable clock network for programmable logic device | Kang Wei Lai, Richard Yen-Hsiang Chang | 2013-05-14 |
| 8364738 | Programmable logic device with specialized functional block | Martin Langhammer, Leon Zheng, Chiao Kai Hwang | 2013-01-29 |
| 8253484 | Configurable clock network for programmable logic device | Kang Wei Lai, Richard Yen-Hsiang Chang | 2012-08-28 |
| 8072260 | Configurable clock network for programmable logic device | Kang Wei Lai, Richard Yen-Hsiang Chang | 2011-12-06 |
| 7859329 | Configurable clock network for programmable logic device | Kang Wei Lai, Richard Yen-Hsiang Chang | 2010-12-28 |
| 7698358 | Programmable logic device with specialized functional block | Martin Langhammer, Leon Zheng, Chiao Kai Hwang | 2010-04-13 |
| 7646237 | Configurable clock network for programmable logic device | Kang Wei Lai, Richard Yen-Hsiang Chang | 2010-01-12 |
| 7623609 | Dynamic phase alignment methods and apparatus | Richard Yen-Hsiang Chang | 2009-11-24 |
| 7453968 | Dynamic phase alignment methods and apparatus | Richard Yen-Hsiang Chang | 2008-11-18 |
| 7437401 | Multiplier-accumulator block mode splitting | Leon Zheng, Martin Langhammer, Steven Perry, Paul Metzgen, William Hwang +1 more | 2008-10-14 |
| 7346644 | Devices and methods with programmable logic and digital signal processing regions | Martin Langhammer, Chiao Kai Hwang | 2008-03-18 |
| 7307459 | Programmable phase-locked loop circuitry for programmable logic device | — | 2007-12-11 |
| 7286007 | Configurable clock network for programmable logic device | Kang Wei Lai, Richard Yen-Hsiang Chang | 2007-10-23 |
| 7276943 | Highly configurable PLL architecture for programmable logic | Wanli Chang, Kang Wei Lai, Mian Z. Smith, Richard Yen-Hsiang Chang | 2007-10-02 |
| 7242229 | Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode | Richard Yen-Hsiang Chang, Edward Aung | 2007-07-10 |
| 7216139 | Programmable logic device including multipliers and configurations thereof to reduce resource utilization | Martin Langhammer, Chiao Kai Hwang | 2007-05-08 |
| 7193443 | Differential output buffer with super size | Mian Z. Smith | 2007-03-20 |
| 7180334 | Apparatus and method for decreasing the lock time of a lock loop circuit | — | 2007-02-20 |
| 7142010 | Programmable logic device including multipliers and configurations thereof to reduce resource utilization | Martin Langhammer, Chiao Kai Hwang | 2006-11-28 |
| 7119576 | Devices and methods with programmable logic and digital signal processing regions | Martin Langhammer, Chiao Kai Hwang | 2006-10-10 |
| 7098707 | Highly configurable PLL architecture for programmable logic | Wanli Chang, Kang Wei Lai, Mian Z. Smith, Richard Yen-Hsiang Chang | 2006-08-29 |
| 7075365 | Configurable clock network for programmable logic device | Kang Wei Lai, Richard Yen-Hsiang Chang | 2006-07-11 |